Sharp rise-and-fall time,high-amplitude pulse generator

ABSTRACT

A pulse circuit switches in response to a bipolar digital logic input pulse to provide a sequential on-drive off-drive current thru low-impedance charge and discharge paths to drive an output semiconductor circuit. The output semiconductor circuit responds to the on-drive off-drive current and switches to provide a lowimpedance charge path for a high-amplitude, high-speed output current pulse.

United States Patent Jon M. Surprise Mogadore;

Charles D. Blust, Stow, both 0! Ohio 795,799

Feb. 3, 1969 Sept. 28, 1971 Goodyear Aerospace Corporation Akron, OhioInventors Appl. No. Filed Patented Assignee SHARP RlSE-AND-FALL TIME,iiETI A MPLITUDE PULSE GENERATOR 6 Claims, 1 1 Drawing Figs.

US. Cl 307/263, 307/246, 307/254, 307/268, 330/30 D Int. Cl "03k 5/12Field of Search 307/246, 254, 255, 260, 262, 263, 268, 270, 215; 330/30D References Cited UNITED STATES PATENTS 3,077,566 2/1963 Vosteen 330/30D X 3,292,098 12/ 1966 Bensing 330/30 D X 3,396,282 8/1968 Sheng et a1.307/215 X 3,416,003 12/1968 Walker 307/207 3,435,359 3/1969 Sennhenn.330/30 D X 3,065,358 11/1962 Lee et a1. 307/270 X 3,174,054 3/1965Wortzman.... 307/254 X 3,192,401 6/1965 Gray 307/260 3,244,910 4/1966Leifer 307/254 3,469,111 9/1969 Peters et al. 307/246 X OTHER REFERENCESPUB 1 Low Impedance Switch Circuit" by Gillett in IBM TechnicalDisclosure Bulletin, Vol. 7, No. 6, November 1964 Page 440 PrimaryExaminer-Stanley D. Miller, Jr. Attorneys-J. G. Pcre and L. A. GermainABSTRACT: A pulse circuit switches in response to a bipolar digitallogic input pulse to provide a sequential on-drive offdrive current thrulow-impedance charge and discharge paths to drive an outputsemiconductor circuit. The output semiconductor circuit responds to theon-drive off-drive current and switches to provide a low-impedancecharge path for a highamplitude, high-speed output current pulse.

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' LOAD g CURRENT i INVENTORS 2 CHARLES D. BLUST 5 JON M. SURPRISE AGENT0 lb z'o'ioiosbs'o 'TIME NANOSECONDS PATENTEDSEP28|97| 3,609,405 SHEET 2OF 2 I0 LOGIC REFERENCE INPUT- VOLTAGE Vr FIG. 3

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l 400 Q lJ-l CURRENT S j 2 0 lb 2'0 a'o4'o s'oo 'r'os'o 9'0 TIMENANOSECONDS INVENTORS CHARLES D. BLUST' JON M. SURPRISE AGENT SIIARPRlSE-AND-FALL TIME, HIGH-AMPLITUDE PULSE GENERATOR This inventionrelates generally to switching circuits and signal generators and morespecifically to a pulse-generating circuit employing semiconductordevices.

It is general object of this invention to provide an electronicswitching circuit which generates high-current amplitude pulses withmaximum speed, efficiency, low power dissipation, and a minimum numberof components.

Another object of this invention is to provide output pulses having asharp rise-and-fall time and very short pulse width.

Still another object is to provide a high-speed electronic switchingcircuit having a bipolar drive scheme which provides both ondrive andoff-drive current such that the maximum available current is used todrive the output in both drive-on and drive-off modes of operation.

Another object of this invention is to provide a high-speed switchingcircuit which lends itself to integrated circuit techniques resulting inminiaturization of the circuit. These objects and other objects andadvantages of the invention will become apparent from the followingdescription and accompanying drawings of the preferred embodiments ofthe invention.

In the drawings:

Fig. l is a schematic circuit diagram of one embodiment of theinvention.

FIG. 2A through 2F are the waveforms associated with the circuit of FIG.1.

FIG. 3 is a schematic circuit diagram of another embodiment of theinvention.

FIG. 4A through 4C are the waveforms associated with the circuit of FIG.3.

With reference to the form of the invention shown in FIG. 1, a circuitis provided including a first pair of NPN-type transistors 12 and 14having respective base, emitter, and collector electrodes. The emittersl6 and 18 are commonly connected through a resistor 20 to a source ofnegative DC potential E, at 22. The potential source E and resistor 20combine to form a substantially constant current source. The collectors24 and 26 of transistors 12 and 14 respectively, are connected throughtheir respective resistances 30 and 32 to a source of positive DCpotential E at 28. The base 36 of transistor 14 is connected to a sourceof constant level DC voltage 34 which will hereinafter be referred to asa reference voltage V,. The base 40 of transistor 12 is connected to asource of digital logic-input pulses 10. The logic-input pulses arereadily available in most digital equipments and are within theknowledge of persons skilled in the art. The circuit herebeforedescribed including transistors 12 and 14, is also a well-knownhigh-speed digital circuit described and claimed in U.S. Pat. No.2,964,652 to II. S. Yourke as a current switch." The outputs of thecurrent switch are taken off the collectors 24 and 26 via conductors 38and 41 respectively.

Connected to the outputs of the current switch are a second pair ofNPN-type transistors 42 and 44 having respective base, emitter andcollector electrodes. The base 46 of transistor 42 is connected viaconductor 38 to the collector 24 of transistor 12, and the base 48 oftransistor 44 is connected via conductor 41 to the collector 26 oftransistor 14. Transistor 44 has its collector 56 connected to thesource of positive DC potential E, at 28, while transistor 42 has itscollector 54 connected to the emitter 52 of transistor 44. The emitter50 of transistor 42 is ground connected. The output of this circuit istaken at 58 to which is connected, through a coupling element 60, anoutput semiconductor 62. The semiconductor 62 is a PNP-type transistorhaving its base 64 connected to the output side of the coupling element60 and to the potential E; at 70 through the base bias resistor 72. Theemitter 66 is connected to potential E, and the collector 68 isconnected to ground potential through load 71. The coupling element 60is shown and described in this embodiment as a capacitor, however, othercomponents such as zener diodes will work as well and all within theknowledge of persons skilled in the art.

In operation, the circuit of FIG. 1 accepts a logic input having avoltage level normally more positive than the level of the voltagereference V, Transistor 12 of the current switch is normally conductiveand its collector is at substantially ground potential. Transistor 42,by virtue of its base being at the same potential as collector 24 oftransistor 12, is OFF or nonconducting. Transistor 14 of the currentswitch has its base-emitter junction reverse biased and is normally OFF,and its collector 26 is at substantially the potential of DC source ETransistor 44, having its base at the same potential as collector 26 oftransistor 14, is ON and provides a low impedance charge path for thecapacitive element 60. Base 64 of transistor 62 is normally at thepotential of DC source 5;, and is normally OFF. The state of the circuitwhen the logic input is more positive than V, is clearly shown in thewaveforms of FIG. 2A through 2F.

When the logic input is a negative-going pulse which drops to a levelmore negative than V, as shown in FIG. 2A, transistor 12 is cut OFF andthe emitter base junction of transistor 14 becomes forward biased due tothe potential of source E and transistor 14 is turned ON. The collector26 of transistor 14 drops to substantially ground potential cutting OFFtransistor 44 and the charge supply for capacitance 60. The collector 24of transistor 12 and also the base 46 of transistor 42 have a risingpotential and transistor 42 is turned ON providing a low-impedancedischarge path for capacitance 60.

Since the discharge path for capacitance 60 is a very low impedance, thebase drive to transistor 62 is high causing it to turn ON rapidly. Thisrapid turn ON of transistor 62 results in a step output having a risetime on the order of 10 nanoseconds as shown in FIG. 2F.

At the end of the logic-input pulse, transistor 12 is turned ON with theresulting cut OFF of transistor 42 and the discharge path forcapacitance 60. Transistor 14 is cut OFF with the resulting turning ONof transistor 44 and subsequent recharging of capacitance 60. Transistor62 is cut OFF resulting in an output pulse to the load 71 having veryfast rise and fall times, and a pulse width in the nanosecond range.

The circuit of FIG. 1 having the'component values listed below, andconnected to a ISO-ohm load, provided an output pulse having a rise timeof 10 nanoseconds, a pulse width of 48 nanoseconds measured at the 50percent points, and an amplitude of approximately 290 milliamperes.

Logic Input Pulse Range VDC 0.7 to

l .5 V, (34) VDC l.l5 E, (22) VDC $.2 E, (28) VDC +5.0 5, 70 g VDC +s0.oTransistors (NPN TYPE) (l2) 2N9l8 (l4) 2N9 l 8 (42) 2N9 l 8 (44] 2N9l8Transistor (PNP TYPE) (62) 2N2905A Capacitance (6) picoi'arads 470Resistors ohms (30) 550 ohms (32) 59l ohms (20) 386 ohms (72) 470 Amodified fonn of the circuit of FIG. 1 is shown in FIG. 3 and itsassociated waveforms are shown in FIGS. 4A through 4C. In throughembodiment the logic input is normally more negative than V, and apositive-going logic-input pulse alternately switches transistors 12 and14 as hereinbefore described. The capacitive element 60 and the outputtransistor 62 are replaced by an NPN-type transistor 74 which is directcoupled or base connected to the output at 58. The emitter 76 is groundconnected and the collector 78 is connected through a load 82 to asource of positive DC potential E, at 84.

' In operation, transistor 74 is driven ON or OFF by the sequentialon-drive current supplied to its base 80 by the switching of transistors42 and 44. As shown in FIG. 4C, an output pulse having a currentamplitude of approximately 400 milliamperes, rise and fall times ofabout nanoseconds, and a pulse width of 45 nanoseconds is supplied to an80-ohm load 82 when NPN-type 2N32S2 transistor, having its collectorcircuit biased by a positive 32 volt DC source potential E is used inthe output circuit.

Thus, it has been shown that the invention provides a switching circuitwhich utilizes the very low impedance paths of transistors 42 and 44 tosupply the maximum available current to an output semiconductor in bothdrive-on and drive-off modes of operation to provide high-speed currentpulses at the output, and while the invention has been particularlyshown and described with reference to the preferred embodiments, it willbecome apparent to those skilled in the art that various outputs i.e.,positive or negative going pulses, spike pulses, narrow or wide pulses,etc., may be achieved by the choice of transistors and biasing levelused, and the various logic inputs available. It will also becomeapparent to one skilled in the art that circuits herein described arereadily adapted to integrated circuit techniques and may be sofabricated for low power dissipation and miniaturization of the circuitwithout deviating from the spirit of the invention.

What is claimed is:

l. A pulse-switching circuit comprising:

a. a reference voltage source;

b. a source of logic pulses bipolar with respect to the referencevoltage source;

c. bias voltage means;

d. first pair semiconductor means having base, emitter, and collectorelectrodes, one of the pair base connected to the source of logicpulses, the other of the pair base connected to the reference voltagesource, the collectors of the pair connected to the bias voltage means,and the pair interconnected at their emitters and to the bias voltagemeans wherein a current is effected to flow in one of the pair when thelogic pulse is positive with respect to the reference voltage, and inthe other of the pair when the logic pulse is negative with respect tothe reference voltage;

e. second pair semiconductor means having base, emitter,

and collector electrodes, one of the pair having its collector connectedto the bias voltage means and its base connected to the collector of oneof the first pair semiconductor means while the other of the pair iscommonemitter connected and has its base connected to the collector ofthe other of said first semiconductor means, said second pairsemiconductor means interconnected at the remaining emitter-collectorelectrodes to effect an ondrive off-drive output current at saidinterconnection in response to the alternate and sequential current flowin the first pair semiconductor means; and

. output semiconductor means having base, emitter, and collectorelectrodes, said means base connected to the emitter collectorinterconnection of the second pair semiconductor means and responsive tothe on-drive offdrive output of the second pair semiconductor means, andthe collector-emitter circuit biased to provide highspeed,high-amplitude current pulses when switched into conduction.

2. The switching circuit of claim 1 wherein the output semiconductormeans is an NPN-type transistor in a commonemitter configuration.

3. The switching circuit of claim 1 wherein:

a. the output semiconductor means is a PNP-type transistor;

and

b. a capacitor couples the base of said transistor to theemitter-collector interconnection of the second pair semiconductor meansand which capacitor responds to the on-drive off-drive current of saidsecond pair semiconductor means to drive the output semiconductor intoeithercutofforconduction. 4. A switching circuit compnsmg incombination, four transistors of like conductivity type and an outputtransistor each having base, emitter, and collector electrodes, a sourceof collector emitter bias voltage, a source of reference voltage, asource of bipolar input pulses, means coupling the base of a first ofsaid transistors to the source of reference voltage, means coupling thebase of a second of said transistors to the source of bipolar inputpulses, means coupling the collectors of said first and secondtransistors to the bias voltage, means intercoupling the emitters ofsaid first and second transistors so that they operate as an emittercoupled pair wherein current flows in one of the pair when the input ispositive with respect to the reference voltage and in the other of thepair when the input is negative with respect to the reference voltage,means coupling the base of a third of said transistors to the collectorof said second transistor, said third transistor in a common emitterconfiguration, means coupling the base of the fourth of said transistorsto the collector of said first transistor, means coupling the collectorof said fourth transistor to the bias voltage, means coupling the baseof said output transistor to the collector of said third transistor andto the emitter of said fourth transistor such that said outputtransistor is driven into either of its conductivity states by theswitching of the third and fourth transistors, said output transistorhaving its collector emitter circuit biased to provide high-speed,high-amplitude pulses to an output terminal.

5. The circuit of claim 1 wherein the output transistor is an NPN-typesemiconductor.

6. The circuit of claim 1 wherein the output transistor is a PNP-typesemiconductor and a capacitor couples its base electrode to the emittercollector intercoupled third and fourth transistors to charge anddischarge in response to the third and fourth transistor switching andproviding on-drive off-drive current to drive the output transistor intoeither of its states of conductivity.

, UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3()()9 4Q5 Dated g g per 2g, 1971 ln fl Jon M. Surprise and Charles D.Blust It is certified that error appears in the above-identified patentand that said Letters Patent are hereby corrected as shown below:

Column 2, line 65, after "In" change through" to this--.

Column 2, line 75, after "on-drive" insert off-dr ive Column 4, Claim 5,line 45, after "claim" change "1" to --4--.

Column 4, Claim 6, line 47, after "claim" change '1" to -4--.

Signed and scaled this 18th day of April 1972.

(SEAL) Attest:

HDIJJWD ILPL =E'PCIIJQR,JL1. B RT G TSGImUl Attosti n OfficerCommissioner. of Patents QRM PO-lOSD (10-69) USCOMM-Dc 60375.;259

E u 5 GOVERNMENT unmnc Orncc IQODO-JSG-LH

1. A pulse-switching circuit comprising: a. a reference voltage source;b. a source of logic pulses bipolar with respect to the referencevoltage source; c. bias voltage means; d. first pair semiconductor meanshaving base, emitter, and collector electrodes, one of the pair baseconnected to the source of logic pulses, the other of the pair baseconnected to the reference voltage source, the collectors of the pairconnected to the bias voltage means, and the pair interconnected attheir emitters and to the bias voltage means wherein a current iseffected to flow in one of the pair when the logic pulse is positivewith respect to the reference voltage, and in the other of the pair whenthe logic pulse is negative with respect to the reference voltage; e.second pair semiconductor means having base, emitter, and collectorelectrodes, one of the pair having its collector connected to the biasvoltage means and its Base connected to the collector of one of thefirst pair semiconductor means while the other of the pair iscommon-emitter connected and has its base connected to the collector ofthe other of said first semiconductor means, said second pairsemiconductor means interconnected at the remaining emitter-collectorelectrodes to effect an on-drive off-drive output current at saidinterconnection in response to the alternate and sequential current flowin the first pair semiconductor means; and f. output semiconductor meanshaving base, emitter, and collector electrodes, said means baseconnected to the emitter collector interconnection of the second pairsemiconductor means and responsive to the on-drive off-drive output ofthe second pair semiconductor means, and the collector-emitter circuitbiased to provide high-speed, high-amplitude current pulses whenswitched into conduction.
 2. The switching circuit of claim 1 whereinthe output semiconductor means is an NPN-type transistor in acommon-emitter configuration.
 3. The switching circuit of claim 1wherein: a. the output semiconductor means is a PNP-type transistor; andb. a capacitor couples the base of said transistor to theemitter-collector interconnection of the second pair semiconductor meansand which capacitor responds to the on-drive off-drive current of saidsecond pair semiconductor means to drive the output semiconductor intoeither cutoff or conduction.
 4. A switching circuit comprising incombination, four transistors of like conductivity type and an outputtransistor each having base, emitter, and collector electrodes, a sourceof collector emitter bias voltage, a source of reference voltage, asource of bipolar input pulses, means coupling the base of a first ofsaid transistors to the source of reference voltage, means coupling thebase of a second of said transistors to the source of bipolar inputpulses, means coupling the collectors of said first and secondtransistors to the bias voltage, means intercoupling the emitters ofsaid first and second transistors so that they operate as an emittercoupled pair wherein current flows in one of the pair when the input ispositive with respect to the reference voltage and in the other of thepair when the input is negative with respect to the reference voltage,means coupling the base of a third of said transistors to the collectorof said second transistor, said third transistor in a common emitterconfiguration, means coupling the base of the fourth of said transistorsto the collector of said first transistor, means coupling the collectorof said fourth transistor to the bias voltage, means coupling the baseof said output transistor to the collector of said third transistor andto the emitter of said fourth transistor such that said outputtransistor is driven into either of its conductivity states by theswitching of the third and fourth transistors, said output transistorhaving its collector emitter circuit biased to provide high-speed,high-amplitude pulses to an output terminal.
 5. The circuit of claim 1wherein the output transistor is an NPN-type semiconductor.
 6. Thecircuit of claim 1 wherein the output transistor is a PNP-typesemiconductor and a capacitor couples its base electrode to the emittercollector intercoupled third and fourth transistors to charge anddischarge in response to the third and fourth transistor switching andproviding on-drive off-drive current to drive the output transistor intoeither of its states of conductivity.